Synchronous memory devices such as synchronous static random access memory (SRAM) devices are generally designed to operate as fast as possible. One component of the performance of the memory device is the time that it takes the input path circuitry to decode and latch an address for the memory device.
FIG. 1 shows a conventional address input path circuit 100. Address signals received from an address bus are supplied to input buffer 102, decoded by decoder 104, and then provided to register 106. Register 106 latches the decoded address in response to an edge transition of a clock pulse signal output from clock pulse generator 110. Clock pulse generator 110 generates the internal clock pulse in response to an external clock signal CLK provided to clock buffer 108.
Register 106 must receive a clock signal during the time in which decoder 104 is outputting the decoded address. There is typically a set-up time for circuit 100 in which the address input to input buffer 102 must be stable prior to a transition of CLK. There is also typically a hold time for circuit 100 in which the address input to input buffer 102 must be stable following a transition of CLK. The set-up and hold time window ensures that register 106 will latch the decoded address when clock pulse generator 110 provides the clock pulse signal to register 106. It is desirable to keep the set-up and hold time window small such that the address input path circuit 100 is as fast as possible. In practice, however, it is often necessary to provide a fairly long set-up and hold time window to account for any timing differences or skew caused by decoder 104. For example, address input path circuit 100 must accommodate all possible address input signal logic states including all zeros, a mixture of ones and zeros, and all ones. Any timing differences between the decoding of the different address input signals is generally compensated for by providing a correspondingly longer set-up and hold time window resulting in degradation of the performance of the address input path circuit 100. Additionally, system designers generally prefer integrated circuits that have reduced or tight set-up and hold time windows.
Decoder 104 typically includes a number of NAND gates and/or NOR gates to decode an address. FIG. 2 shows a conventional two-input complementary metal oxide semiconductor (CMOS) NAND gate 200 that may be used in decoder 104. NAND gate 200 includes a pair of p-channel MOS (PMOS) transistors 202 and 204 connected in parallel with each other, and connected between a power source VDD and an output VOUT. NAND gate 200 also includes a pair of n-channel MOS (NMOS) transistors 206 and 208 connected in series with each other and coupled between VOUT and ground.
NAND gate 200 will drive VOUT to a low logic state (low) when both of inputs signals INA and INB are at a high logic state (high). NAND gate 200 will drive VOUT high when INA, INB, or INA and INB are low. The amount of time required for NAND gate 200 to drive VOUT high (low-to-high output slew rate) depends on whether INA and INB are both low, or if only one of INA or INB is low. For example, when INA transitions from a high state to a low state while INB is held high, VOUT is pulled high through only one of the PMOS transistors, namely, PMOS transistor 202. Similarly, when INB transitions from a high state to a low state while INA is held high, VOUT is pulled high by only PMOS transistor 204. On the other hand, if both INA and INB transition from high to low states, VOUT is pulled high through both of PMOS transistors 202 and 204. Two PMOS transistors generally pull VOUT to a high state faster than one PMOS transistor. For example, if PMOS transistors 202 and 204 are similarly sized to provide approximately equal amounts of current, the rising slew rate of VOUT may be approximately twice as fast when both of PMOS transistors 202 and 204 are on as opposed to when only one of PMOS transistors 202 or 204 is on. Thus, timing skew differences may exist between NAND gates in decoder 104 that receive different states of input signals, and this may increase the set-up and hold time window for address input patch circuit 100.
FIG. 3 shows another conventional two-input NAND gate 300 that includes PMOS transistor 302 coupled between VOUT and PMOS transistors 202 and 204. PMOS transistor 302 is always on because its gate is coupled to ground. PMOS transistor 302 chokes the flow of current from the power supply to VOUT to reduce the speed at which VOUT is pulled to a high state by PMOS transistor 202 and/or 204. PMOS transistor 302 is typically sized smaller than PMOS transistors 202 and 204 so that the charging of VOUT to a high state is primarily controlled by PMOS transistor 302. This generally reduces the difference between the slew rates of VOUT when pulled high by only one of PMOS transistors 202 or 204 as opposed to VOUT being pulled high by both of PMOS transistors 202 and 204. For example, the rising slew rate of VOUT may be approximately 10 to 50 percent faster when both of PMOS transistors 202 and 204 are on as opposed to when only one of PMOS transistors 202 or 204 is on. Thus, timing skew differences may still exist when decoder 104 uses NAND gates such as NAND gate 300.
FIG. 4 shows a conventional two-input NAND gate 400 that provides symmetry in the slew rate of VOUT when VOUT is switching from a high state to a low state. NAND gate 400 includes another pair of NMOS transistors 402 and 404 coupled in series with each other, and coupled in parallel with the NMOS transistors 206 and 208 between VOUT and ground. NMOS transistor 402 has its gate coupled to input signal INB, and NMOS transistor 404 has its gate coupled to input signal INA. NAND gate 400 will generally cause VOUT to be driven low at the same slew rate regardless of whether input signal INA or INB is driven high first. For example, if INA is driven high before INB in NAND gate 200 of FIG. 2, then node 207 will be driven to one threshold drop below the voltage level of input signal INA. When INB is driven high some internal time later, NMOS transistor 208 must then discharge node 207, and then discharge VOUT to ground. If, however, INB is driven high before INA is driven high, then NMOS transistor 208 pulls node 207 to ground, and then NMOS transistor 206 pulls VOUT to ground. Thus, it is preferable that INA and INB are simultaneously driven to a high state, or that INB is driven high before INA. The addition of NMOS transistors 402 and 404 ensure that one of the NMOS transistor 208 or 404 will turn on first before a corresponding one of NMOS transistors 206 and 402 turn on when INA and INB are high.
FIG. 5 shows a conventional CMOS NOR gate 500 that may be used in decoder 104. NOR gate 500 includes a pair of PMOS transistors 502 and 504 coupled in series with each other and coupled between VDD and VOUT. NOR gate 500 also includes a pair of NMOS transistors 506 and 508 coupled in parallel with each other and coupled between VOUT and ground.
NOR gate 500 will drive VOUT to a high logic state when both of inputs signals INA and INB are at a low logic state. NOR gate 500 will drive VOUT low when INA, INB, or INA and INB are high. The amount of time required for NOR gate 500 to drive VOUT low (high-to-low output slew rate) depends on whether INA and INB are both high, or if only one of INA or INB is high. For example, when INA transitions from a low state to a high state while INB is held low, VOUT is pulled low through only one of the NMOS transistors, namely, NMOS transistor 506. Similarly, when INB transitions from a low state to a high state while INA is held low, VOUT is pulled low through only NMOS transistor 508. On the other hand, if both INA and INB transition from low to high states, VOUT is pulled low through both of NMOS transistors 506 and 508. Two NMOS transistors generally pull VOUT to a low state faster than one NMOS transistor. Thus, timing skew differences may exist between NOR gates in decoder 104 that receive different states of input signals, and this may increase the set-up and hold time window for address input patch circuit 100.
FIG. 6 shows another conventional two-input NOR gate 600 that includes NMOS transistor 602 coupled between VOUT and NMOS transistors 506 and 508. NMOS transistor 602 has its gate coupled to VDD and is always on. As with PMOS transistor 302 of FIG. 3, NMOS transistor 602 chokes the flow of current from VOUT to ground to reduce the speed at which VOUT is pulled to a low state by NMOS transistors 506 and 508. This generally reduces the difference between the slew rates of VOUT when pulled low by only one of NMOS transistors 506 or 508 as opposed to VOUT being pulled low by both of NMOS transistors 506 and 508.
FIG. 7 shows a conventional two-input NOR gate 700 that provides symmetry in the slew rate of VOUT when VOUT is switching from a low state to a high state. NOR gate 700 includes another pair of PMOS transistors 702 and 704 coupled in series with each other, and coupled in parallel with PMOS transistors 502 and 504 between VDD and VOUT. PMOS transistor 702 has its gate coupled to input signal INB, and PMOS transistor 704 has its gate coupled to input signal INA. As with NMOS transistors 402 and 404 of FIG. 4, PMOS transistors 702 and 704 will generally cause VOUT to be driven high at the same slew rate regardless of whether input signal INA or INB is driven low first.
Therefore, it is desirable to reduce the set-up and hold time window of an address input path circuit of a synchronous or asynchronous device by reducing the difference in the output slew rates of the logic gates that are used in a decoder circuit of the address input path.